/*
 * Copyright (c) 2022, IMMORTA Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * - Neither the name of IMMORTA Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


#ifndef MPU_DRV_H
#define MPU_DRV_H

/*!
 * @file mpu_drv.h
 * @brief mpu driver header file
 */

/*!
 * @addtogroup cortex_drv
 * @{
 */

/*******Includes***************************************************************/
#include "device_registers.h"

/*******Definitions************************************************************/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
  * @{
  */
#define MPU_HFNMI_PRIVDEF_NONE    (0x00000000U)
#define MPU_HARDFAULT_NMI         (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT    (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF         (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
  * @{
  */
#define MPU_REGION_ENABLE    ((uint8_t)0x01)
#define MPU_REGION_DISABLE   ((uint8_t)0x00)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
  * @{
  */
#define MPU_INSTRUCTION_ACCESS_ENABLE    ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE   ((uint8_t)0x01)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
  * @{
  */
#define MPU_ACCESS_SHAREABLE       ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE   ((uint8_t)0x00)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
  * @{
  */
#define MPU_ACCESS_CACHEABLE       ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE   ((uint8_t)0x00)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
  * @{
  */
#define MPU_ACCESS_BUFFERABLE      ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE  ((uint8_t)0x00)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
  * @{
  */
#define MPU_TEX_LEVEL0    ((uint8_t)0x00)
#define MPU_TEX_LEVEL1    ((uint8_t)0x01)
#define MPU_TEX_LEVEL2    ((uint8_t)0x02)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
  * @{
  */
#define MPU_REGION_SIZE_256B         ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B         ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB          ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB          ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB          ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB          ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB         ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB         ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB         ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB        ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB        ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB        ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB          ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB          ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB          ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB          ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB         ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB         ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB         ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB        ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB        ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB        ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB          ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB          ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB          ((uint8_t)0x1F)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
  * @{
  */
#define MPU_REGION_NO_ACCESS          ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW            ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO        ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS        ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO            ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO        ((uint8_t)0x06)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
  * @{
  */
#define MPU_REGION_NUMBER0            ((uint8_t)0x00)
#define MPU_REGION_NUMBER1            ((uint8_t)0x01)
#define MPU_REGION_NUMBER2            ((uint8_t)0x02)
#define MPU_REGION_NUMBER3            ((uint8_t)0x03)
#define MPU_REGION_NUMBER4            ((uint8_t)0x04)
#define MPU_REGION_NUMBER5            ((uint8_t)0x05)
#define MPU_REGION_NUMBER6            ((uint8_t)0x06)
#define MPU_REGION_NUMBER7            ((uint8_t)0x07)
/**
  * @}
  */

/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
  * @brief  MPU Region initialization structure
  * @{
  */
typedef struct {
    uint8_t Enable;                /*!< Specifies the status of the region.
                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                */
    uint8_t Number;                /*!< Specifies the number of the region to protect.
                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                */
    uint32_t BaseAddress;          /*!< Specifies the base address of the region to protect.
                                                                                                                    */
    uint8_t Size;                  /*!< Specifies the size of the region to protect.
                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                  */
    uint8_t SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.
                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF   */
    uint8_t TypeExtField;          /*!< Specifies the TEX field level.
                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                   */
    uint8_t AccessPermission;      /*!< Specifies the region access permission type.
                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
    uint8_t DisableExec;           /*!< Specifies the instruction access status.
                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access           */
    uint8_t IsShareable;           /*!< Specifies the shareability status of the protected region.
                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable             */
    uint8_t IsCacheable;           /*!< Specifies the cacheable status of the region protected.
                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable             */
    uint8_t IsBufferable;          /*!< Specifies the bufferable status of the protected region.
                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable            */
} mpu_region_config_t;
/**
  * @}
  */
#endif /* __MPU_PRESENT */


/*******APIs*******************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif

/*!
 * @brief Enable the MPU
 *
 * @param[in] MPU_Control: Specifies the control mode of the MPU during hard fault,
 *            NMI, FAULTMASK and privileged access to the default memory
 *            This parameter can be one of the following values:
 *            - MPU_HFNMI_PRIVDEF_NONE
 *            - MPU_HARDFAULT_NMI
 *            - MPU_PRIVILEGED_DEFAULT
 *            - MPU_HFNMI_PRIVDEF
 * @return None
 */
void MPU_Enable(uint32_t mpuControl);

/*!
 * @brief Disable the MPU
 *
 * @param[in] None
 * @return None
 */
void MPU_Disable(void);

/*!
 * @brief Initialize and configure the Region and the memory to be protected
 *
 * @param[in] regionConfig: Pointer to a mpu_region_config_t structure that contains
 *                          the initialization and configuration information
 * @return None
 */
void MPU_ConfigRegion(mpu_region_config_t* regionConfig);

#if defined(__cplusplus)
}
#endif

/*! @} */

#endif /* MPU_DRV_H */

/*******EOF********************************************************************/
